All signals except Reset, Interrupt are sampled at rising edge of clock.
Operation:
A bus transaction is followed by an address phase followed by one or more data phases. Address phase starts when FRAME# is asserted. For read operation TRDY#(target ready) is asserted. For write operation IRDY#(initiator ready) is asserted. Data phase completes on any clock both IRDY#, TRDY# are asserted. Wait cycles are inserted until both are asserted together.
Address, Data pins are multiplexed. C/BE# pins are multiplexed. They define bus command for address phase, byte enable for data phase. STOP# signal indicates the current target is requesting the master to stop the current transaction. LOCK# used for atomic operations. IDSEL (Initialization Device select) used as chip select for configuration read, write transactions. DEVSEL# indicates whether any device on the bus is selected. Arbitration signals (REQ#, GNT#) of bus master: request, grant access to bus provided RST# is de-asserted.
PAR – even parity signal; has same timing of address/data but delayed by one clock. PAR is driven by master for address, write data phases, and by slave for read data phases. PERR#, SERR# report data parity error, system error(address/command) respectively.
M66EN indicates 33MHz or 66MHz. ACK64# acknowledges 64 bit transfer.
Optional Signals:
INTA#, INTB#, INTC#, INTD# -- request interrupt. PRSNT indicates the motherboard presence of add-in board. CLKRUN# indicates status of CLK. PME -- asynchronous signal used to request a change is system power state. 3.3VAUX -- auxiliary power source. TCK, TDI, TDO, TMS, TRST# -- JTAG signals
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