Logic Families Voltage Translation

No Translation required for the following:

[TTL] to [TTL]

[TTL] to [CMOS with input switching at TTL levels]

[CMOS 5V] to [TTL]

Translation required for the following:

[TTL] to [CMOS*]

Pull up of 1k to 2k required

TTL outputs 2.4V to 3.3V for a high level

CMOS required 3.7 for high level.

The pull up resister increases the output voltage (of TTL driver).

[CMOS*] to [TTL]

*The translation depends on the VCC of CMOS device.

[TTL] to [ECL] / [ECL] to [TTL]

TTL to ECL (ECL to TTL) translator along with ECL termination resistors are needed.

[PECL] to [TTL] / [TTL] to [PECL]

PECL is Positive ECL

PECL to TTL (TTL to PECL) translator needed.

[PECL] to [CMOS] / [CMOS] to [PECL]

Same as above, but pull of 1k to 2k is required for CMOS.

[PECL 5V] to [LVDS 5V]

Pull up both +,- signals to 3V through 50E resistors.

[LVPECL 3.3V] to [LVDS 5V]

Pull up both +,- signals to 1.3V through 50E resistors